In this series of tutorials we take a look into the over view of ARM Cortex-M3 processor, I will try to cover fundamentals, registers, operation modes, built-in nested vector interrupt controller, memory map, bus interface, MPU, instruction set, interrupt exceptions, debugging support etc.
I would recommend you guys to get hold of data sheet and user manual of respective microcontroller to learn in depth about it. NXP controllers are well equipped with proper documentation. At the end of this article I have provided links for supporting documents and application notes from NXP.
Before going to further, take a look into this below figure so, that you can understand what is Cortex-M3 processor and what is Cortex-M3 based micro controller.
Key features of Cortex-M3 Core :
- 32-bit micro processor
- It comes with 32-bit data path, 32-bit register bank, and 32-bit memory interface.
- It’s a Harvard architecture(separate instruction bus and data bus)
- It supports fixed number of debugging components.
- Optional MPU(Memory Protection Unit)
- The core pipeline has 3 stages: Instruction Fetch, Instruction Decode and Instruction Execute.
- It enables direct access to single bits of data in a simple system by implementing a technique called Bit-Banding.
- NVIC (Nested Vectored Interrupt Controller) provides the processor outstanding interrupt handling abilities.
What is the use of Harvard architecture??
This architecture allows instructions and data access to take place at the same time. Therefor in Cortex-M3, multiple bus interfaces, each with optimized usage and the ability to be used simultaneously. But don’t expect that we have two separate 32-bit buses so we can have 4GB + 4GB = 8GB of memory space. These two buses share the same memory space.
Over View of Cortex-M3
Take look into the below figure to get an idea what are there in Cortex-M3 processor based microcontroller.
ARM Cortex-M3 Specifications that actually encouraged me to write this series of tutorial
- High Performance
- Two separate instruction and data buses allow simultaneous data and instruction accesses to be performed.
- Thumb-2 instruction set.
- Instruction fetches are 32 bits
- High clock frequency(100 MHz)
- Advanced Interrupt-Handling features
- The built-in NVIC
- Reduced IRQ handling latency (How?? This will be explained later part)
- Interrupt arrangement is flexible(we can change the priority at the time of running also)
- On receipt of NMI request, immediate execution of the NMI handler is guaranteed.
- Low Power consumption
- Low gate count
- Sleeping mode and deep sleeping modes available (SLEEP and SLEEPDEEP)
- System Features
- It provides bit-band operations, byte-invariant big endian mode, and unaligned data accesssupport.
- Advanced fault-handling features
- Optional MPU
- Debug Supports
- Supports JTAG or serial wire debug interface
- processor status or memory contents can be accessedeven when the core is running
- Built-in support for six breakpoints and four watchpoints
- Optional ETM for instruction trace and data trace using DWT
- New debugging features, including fault status registers, new fault exceptions, and Flash Patchoperations, make debugging much easier
- ITM provides an easy-to-use method to output debug information from test code
- PC sampler and counters inside the DWT provide code-profiling information
Friends who are expertise with eight bit 8051 controllers development should try this article provided by NXP for migrating from eight bit microcontrollers to Cortex M3. You can download the document AN237 – Migrating from 8051 to Cortex Microcontrollers
Same time guys whose doing well in ARM7 development should go ahead and grab Migrating from ARM7 to Cortex-M3 (256 KB ) and start with Cortex M3 development for your latest project or may be try and repeat your last project with Cortex M3
In next tutorial we will discuss about different registers and operation modes of Cortex M3 core.
To go to next tutorial of this series click here.