ARM : Example Setting PLL for LPC2148

PLL_Block Diagram

Hi friends this is Partha, this is my second tutorial on Thanks for appreciating my first tutorial here. In this tutorial we are going to talk about clocking the ARM microcontrollers. ARM controllers can be clocked in different ways, using external clock with cycle 50-50, connecting external crystal oscillator, there are several clocking mechanism. Today we are going to discuss about using external crystal with on chip PLL oscillator.

PLL_Block Diagram

PLL_Block Diagram

Let’s have a look the benefits of using this mechanism:

  • System clock can be generated from 10MHz to 25 MHz.
  • PLL (Phase Locked Loop) can be used to multiply frequency to range from 10MHz to 60MHz.
  • PLL generator allows running ARM at high speed even low speed oscillator connected.
  • The most important is you can change the frequency dynamically
  • As minimum divider is 2 so output of PLL will be always 50% duty cycle
  • To speed up the Core clock (CCLK) we need to use the PLL.

When we talk about PLL we need to understand two important registers PLLCON and PLLCFG. PLLCON controls activation and control of PLL. PLLCFG controls multiplier and divider values.  In this tutorial we
are going to study these registers in depth.

What is PLL?

What If we can run a different oscillator with much higher frequency?  Yes we would run another oscillator with much higher frequency and phase then control output frequency by raising or lowering until it matches to a reference frequency and phase. This system is known as Phase –Locked Loop.

In above figure you notice frequency divider, which allows us to get more frequency by multiplying the input frequency.

In LPC2148, we have two dividers; known as M and P. Current controlled oscillator (CCO) has working range of 156 MHz to 320 MHz

Control Register


PLL_control reg


  • PLLE means PLL Enable Bit.
  • It is set to active the PLL and allows it to lock to the requested frequency.


  • PLLC means PLL connect
  • Is set to connect the PLL as clock source. A successful connect requires the PLLE bit set.

Configuration Register:



  • It is PLL configuration register.
  • This register will be having Multiplier (MSEL) and divider (PSEL) values.
  • MSEL(PLL Multiplier Value) is the multiplier value used in calculating the PLL clock frequency.
  • PSEL (PLL Divider Value) is the divider value used in calculating the PLL clock frequency.
  • In this register, [4:0] bits are MSEL bits and [6:5] are PSEL bits. Since, these bits are fixed; we will be having some specific values for these two.


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Admin has over twenty years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles. Working presently as Development Manager in India. A firm Believer in Knowledge grows when it shared.

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  1. Umesh said:

    I am the beginner for LPC2148 programming and i was searching for the tutorials regarding PLL and i found it here, Simply superb explanation. Thanks for this great tutorial.

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