AVR Timers – In depth 16-bit AVR Timer Register


Hi Guys we are here again to finish our pending work. I hope you have understood AVR Timers – In depth timer register 8-bit and hope you have gone through the first tutorial in this series AVR Timers – An introduction.

Without talking about any basic things about Timers we will start with control unit block diagram, in this diagram you can easily notice so many changes compare to 8-bit (Timer0 and Timer2) control unit block diagram.

When you compare here with 8-bit counter unit block diagram, you can easily make out that 16-bit counter is mapped to two 8-bit memory locations. Basically there are two counters as Counter High(TCNT1H) which contains the upper 8-bits and the second one is Counter Low (TCNT1L) which contains the lower 8-bits.

Here CPU is reading or writing 16-bit counter value within one clock cycle via 8-bit data bus. It is quite interesting to understand how CPU dose this.  When the CPU does an access to the TCNT1H I/O location, the CPU accesses the High byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. It means that the TCNT1H Register can only be indirectly accessed by the CPU.

16-bit Timer Registers

TCCR1A

TCCR1A: Timer/Counter1 control Register A

TCCR1B: Timer/Counter1 control Register A

Bit Number

Description

Bit 7 – ICNC1 Input capture noise canceler
Bit 6 – ICES1 Input capture edge select
Bit 5 – RESERVED Reserve Bit
Bit 4:3 – WGM13:2 Wave form generation mode
Bit 2:0 – CS12:0 Clock select

Clock Select Bit Description

Clock select bit

TCNT1H and TCNT1L -Timer/Counter 1 High & Low Register

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers.

TIMSK-Timer/Counter Interrupt Mask Register

As we have discussed earlier tutorial about this and well aware of that it contains interrupt control bits for several Timer/Counters. In this tutorial we are only Timer1 bits are described here. Described bits are colored different in image below.

Bit Number

Description

Bit 5 – TICIE1 Input capture interrupt enable for Timer1
Bit 4 – OCIE1A Output compare A match interrupt enable for Timer1
Bit 3 – OCIE1B Output compare B match interrupt enable for Timer1
Bit 2 – TOIE1 Overflow interrupt enable for Timer1

TIFR-Timer/Counter Interrupt Flag Register

Please check image below, as this register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section.

Bit Number

Description

Bit 5 – ICF1 Input capture flag for Timer1
Bit 4 – OCF1A Output compare A match flag  for Timer1
Bit 3 – OCF1B Output compare B match flag for Timer1
Bit 2 – TOV1 Overflow flag for Timer1

One sincere request to all the readers, please comment down and correct us, this site is trying to help people to understand embedded technology, this is only possible with your comments and corrections. Please subscribe to the newsletter to get latest project/article updates right in your email inbox. Take few moments and like zembedded facebook page, follow on tweeter, thanks!

 

 

Related posts:

About author

This article was written by admin

Admin has over twenty years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles. Working presently as Development Manager in India. A firm Believer in Knowledge grows when it shared.

Comments

No Comments

Leave your comment

Your email address will not be published. Required fields are marked *