AVR Timers – In depth Timer Registers 8-bit

As we have discussed in first tutorial in this series AVR Timers – An Introduction I assume that you have gone through the tutorial and are good enough to understand the basics of AVR timers. If you are strting straight here, then i request you to click here and read the first part

In this tutorial we are going to discuss in depth about different Timer Registers. As we all know you need to manipulate register pins to activate and deactivate different peripherals in Microcontrollers. Here we are only brushing the important part of timers you can actually learn a lot by just going through respective microcontroller’s  datasheets.

In this tutorial we will cover 8-bit Timer (Timer 0 and Timer 2). There are few definitions which we need to know before we start reading datasheet to understand timer/counters in AVR. One request to all the readers there is a lot in datasheet; please follow datasheet for in depth study.

Bottom: The counter reaches the BOTTOM when it becomes 0x00.
:The counter reaches its maximum when it becomes 0xFF (0xFFFF).
TOP: The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be fixed value 'MAX' or the value stored in the OCRx registers(below we are discussing in dept about this register). Assignment of TOP is dependent on the mode of operation as well.

Timer counter clock Source

It can be clocked by an internal or external clock source. The clock source is selected by clock select bits (CS02:0) located in the timer/counter control register (TCCR0). On this selection we have detailed description in our next tutorial.

Counter Unit for 8bit Timer

The main part of 8bit Timer is the programmable bi-direction counter unit , please check the image below (This image is taken from datasheet of Atmega16)


Internal Signal Description

Coutn Increment or decrement TCNT0 by 1
Direction Select between increment and decrement
Clear Clear TCNT0 (set all bits to 0)
Clk Tn Timer/Counter clock, referred to as clkT0 in the following.
TOP Signalize that TCNT0 has reached maximum value.
BOTTOM Signalize that TCNT0 has reached minimum value (zero).

As we know we can generate timer clock can be generated internal or external clock source, depending of the mode of operation used, the counter is cleared, incremented or decremented at each timer clock.

Timer Registers:


  1. 1.    TCCRx

Timer counter control register (TCCRx) contains the counter select bits (CSx2, CSc1, and CSx0)

Bit 7 – FOC0: Force Output Compare.This bit is only active when the WGM00 specifies a non-PWM mode.

Bit 3,6 – WGM0 [1:0]: Waveform Generation Mode.These bit controls the counting sequence of the counter.

Bit 5:4 – COM0 [1:0]: Compare Match Output Mode.These bit controls the output compare pin (OC0) behavior.

Bit 2:0 – COM0 [1:0]: These three clock select bits select the clock source to be used by the timer/counter.

Clock select bit description








No clock source (Timer/Counter stopped).




clkT2S/(No prescaling)




clkT2S/8 (From prescaler)




clkT2S/32 (From prescaler)




clkT2S/64 (From prescaler)




clkT2S/128 (From prescaler)




clkT2S/256 (From prescaler)




clkT2S/1024 (From prescaler)
  1. 2.    Timer / Counter Register – TCNTx:

The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.

  1. 3.    Output Compare Register – OCRx

The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.


  1. 4.    Timer / Counter interrupt Mask Register –  TIMSK

 Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled.         

            Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled.

  1. 5.    Timer / Counter interrupt Flag Register – TIFR

Bit 1 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 – Output Compare Register0.

    Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector.

  1. 6.    Special function IO Register – SFIOR

Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is written to one, the Timer/Counter1 and Timer/Counter0  prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.

If you like this tutorial please clicks like on our face book page and do comment to make us write more practical tutorials. Next part of this tutorial we are going to discuss Timer1 which is of 16-bit timer.

T0 continue next tutorial AVR Timers – In depth 16-bit AVR timer Register part III in timer series click.

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About author

This article was written by admin

Admin has over twenty years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles. Working presently as Development Manager in India. A firm Believer in Knowledge grows when it shared.


Comments (1)
  1. AVR Timers | zembedded says - Posted: January 2, 2013

    […] we finish with introduction of AVR Timers. Please click here  AVR Timers: In depth timer registers 8-bit to continue with this series of […]

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