Cortex-M3: Operation Modes & Access Levels

Thanks for the response you guys have shown in earlier tutorials on Cortex M3 series of microcontrollers. As I always request you, please check the data sheet or user manual for thorough and deep knowledge of NXP ARM controllers. NXP provides a solid documentation and example code support to all their microcontrollers.

In this series of tutorial we are going to discuss Operation modes and access modes of Cortex M3 microcontrollers.

Operation Modes:

Cortex-M3 has two operation modes and two privilege levels.

The operations modes are as follow:

  • Thread mode :

The processor enters Thread mode on reset, or as an exception return. Privileged and unprivileged code can run in Thread mode.

  • Handler mode.

The processor enters Handler mode as a result of an exception. All exceptions are handled in Handler mode. All code is privileged in Handler mode.

The Cortex-M3 supports two operation modes the thread mode for process execution and the handler mode for exception handler’s code, each mode has its own stack pointer, the process stack pointer (PSP) and the main stack pointer (MSP).

Usually the thread and handler modes use the same stack pointer thus sharing the stack memory; however, by configuring the processor to use different stack pointers, the stack memory for those two modes can be separated, consequently protecting the system stack memory form a faulty user process.

As we discussed in earlier tutorial, two stack pointers are banked, that is only one can be accessed at a time, SP accesses the currently used stack pointer.cortex_m3_operationModes1

Access Level:

  • Privileged level
  • User level

The Cortex-M3 supports two access levels, user and privileged access levels, in user level access to certain registers and instructions is restricted and if an MPU is available access to memory regions, containing OS data or another process data, can also be restricted for a user process. This is mainly intended for use by a multitasking OS.

So, what are these operation modes and privilege levels?

Suppose, we are running a normal program, that time an interrupt occurred in between. According to the definition of interrupt word, the normal program has to stop where ever it is and the exception handler has to work. In this, these two modes of operation come into the picture.

When you are running a normal program the operation mode tells that this is Thread mode and when you are running exception handler, then it tells you that, this is Handler mode.

Coming to privilege levels, what exactly they do?

The privilege levels (privileged level and user level) provide a mechanism for safeguarding memory accesses to critical regions as well as providing a basic security model.

When the processor is running a main program (that means processor is in thread mode), it can be either in a privileged state or a user state, but exception handlers can only be in a privileged state. When the processor exits reset, It is in thread mode, with privileged access rights. In the privileged state, a program has access to all memory ranges (except when prohibited by MPU settings) and can use all supported instructions.J

Software in the privileged access level can switch the program into the user access level using the control register. When an exception takes place, the processor will always switch back to the privileged state and return to the previous state when exiting the exception handler. But a user program cannot change back to the privileged state by writing to the control register. It has to go through an exception handler that programs the control register to switch the processor back into the privileged access level when returning to thread mode.

Main use of Privilege levels:

The separation of privilege and user levels improves system reliability by preventing system configuration registers from being accessed or changed by some non trusted programs. If an MPU is available, it can be used in conjunction with privilege levels to protect critical memory locations, such as programs and data for OSs.cortex_m3_operationModes

For example, with privileged accesses, usually used by the OS kernel, all memory locations can be accessed (unless prohibited by MPU setup). When the OS launches a user application, it is likely to be executed in the user access level to protect the system from failing due to a crash of non trusted user programs.

See the next figure you may get a little more clarity about this concept.


Please download Cortex-M3 Technical Reference Manual here. Guys keep commenting below to make this tutorial flawless.  I need you guys support to run this website…please comment and correct me to help others. If you like this article then please like our facebook page here.



Cortex-M3 Technical Reference Manual

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About author

This article was written by admin

Admin has over twenty years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles. Working presently as Development Manager in India. A firm Believer in Knowledge grows when it shared.


Comments (3)
  1. AKD says - Posted: May 20, 2013

    This applies to r2p1 series of M3. What about r1p1 series? If I have to find the mode in r1p1-M3 which registerI should look into?

  2. prashanth says - Posted: November 6, 2014

    Hood explanation..very useful..

  3. FM says - Posted: April 13, 2016

    Thanks for the nice explanations! One questions remains: How to protect the system from non-trusted interrupt handler code (e.g. 3rd party communication stacks)? Is there a way to switch to access level “user” inside a handler before calling the actual non-trusted handler code? Or is the only way to restrict non-trusted handler code the changing of MPU region configurations for privileged code during the first instructions of the handler code, before actually handing control over to the non-trusted handler code?

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