Cortex M3 SysTick Explained Part-I

Hi friend, this is our first tutorial on Cortex-M3, it is going to be a two part tutorial on SysTick, in first part we are going to discuss about SysTick basics and in second part we will be diving deep with SysTic control registers.

The Cortex™ M3 has a timer built into the core called the system timer (SysTick). SysTick is a 24-bits timer specially made available in all ARM Cortex – M3 MCU. Its main purpose is for use to provide a primary timing mechanism that controls the execution of an ARM Cortex – M3 system. SysTick, that counts down from the reload value to zero, reloads, that is wraps to, the value in the SYST_RVR register on the next clock edge, then counts down on subsequent clocks.

Cortex M3 SysTick

The System Tick (SysTick) timer is a basic countdown timer that can be used to generate interrupts at a regular time intervals. And mind it, even when the system is in sleep mode. This makes operating system (OS) porting between Cortex-M3 devices much easier, as there is no need to change the operating system’s system timer’s code. It is implemented as part of Nested Vectored Interrupt Controller (NVIC).

It is suitable for generating a tick for an operating system or for measuring delays. One interesting advantage of having the SysTick in the processor core is the fact that any Cortex™ M3 based processor will operate identically and so it is not necessary to write any more timer code to suit the next chip. A possible exception is when the code uses the SysTick calibration register

Configuring SysTick

  • By default the SysTick is configured for  polling mode.
  • Reload value registers with the interval required between SysTick events.
  • SysTIck Reload Value register supports values between 1 and 0x00FFFFFF.
  • To generate an event at a timed interval, Systick Calibration Value Register can be used to scale value for the Reload Register ( all these registers we are going to see in next part of the tutorial).
  • SysTick Calibration Value Register is a read only register.
  • The Control and Status registers allows to select between polling the timer by reading COUNTFLAG (bit 16) or by the SysTick generating an interrupt.
  • Reading of Control and Status registers clears the COUNTFLAG bit .
  • To generate an interrupt you must TICKINT  (bit 1 of SysTick Control and Status registers) high, enable the appropriate interrupt in Nested Vectored Interrupt Controller (NVIC).
  • To select the core clock set CLKSOURC (bit 2) to 1, and 0 for external reference clock.
  • Set bit 0 of SysTick Control and Status registers for enabling timer.

For more information on SysTick on the Cortex-M3, see the Cortex-M3 technical reference manual from ARM.

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About author

This article was written by admin

Admin has over twenty years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles. Working presently as Development Manager in India. A firm Believer in Knowledge grows when it shared.


Comments (3)
  1. jalaja says - Posted: February 5, 2013

    thanks for this site………. iam getting very usefull information in this site

  2. Cortex M3 SysTick Explained - Part II | zembedded says - Posted: February 26, 2013

    […] I am grateful for overwhelming response that you guys have shown on the first part of Cortex M3 Systickk tutorial. If you just happen to land here, then please have a look of first part here. […]

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