In order to get access to the SDRAM all the parts along the path must be configured correctly to support the specific SDRAM.
This tutorial assumes that you have a basic knowledge on SDRAM. If not, we tried to give you a brief details about SDRAM. Of course it’s not full tutorial on SDRAM description. SDRAM is nothing but Synchronous DRAM.
SDRAM Controller features:
- SDRAM is capable of either 16 bit or 32 bit data path, and supports byte, half word and word access.
- If you consider a specific SDRAM, it will have it’s own device characteristics with respect to timing and command sequence.
- These characteristics are stored into the SDRAM controller and it control the data flow between CPU core and SDRAM.
- SDRAM controller is a part of EBI(Here EBI means External Bus Interface), which is accessed through the system bus from the CPU core.
How to operate & how to connect:
If you are passing a command you need to maintain some amount of delay associated with that command. Of course these delay amount will be different from one to another. You will get the values from it’s data sheet and the timing signals also you will get from data sheet of that particular SDRAM .
- SDRAM is a collection of DRAM memory blocks. Each block call it as Bank.
- A general SDRAM consists 2 banks, some devices have at max 4.
- So, this bank is divided into several number of columns and rows to find out the unique address.
- Instead of using single SDRAM, multiple SDRAMs can be connected together to the SDRAMC to increase the amount of SDRAM available to the system.
- The total size of SDRAM can calculated by the following formula
◦ size = number columns x number of rows x number of blocks
How the Data will be maintained in SDRAM:
The data must be refreshed at intervals to maintain the integrity, because the SDRAM consists data as DRAM blocks. So, from you will get the this interval time?? Yes, you will get the value from your SDRAM data sheet, because it’s different for one SDRAM to other vendor type and specifications of that particular SDRAM.
So, if the data is not refreshed at these regular intervals, then what will happen?
Nothing, the data may become unknown state.
Ok, then, have you observed one word we used several times in above. Which is nothing but, SDRAMC, means SDRAM controller. Now, we discuss what it is? How important it is? And what it will do ?
The SDRAM controller must be configured before using the SDRAM device, because it is the one which will match the time characteristics of the specified device.
Initialization of SDRAMC:
After a reset, the microcontroller is not configured to access the external SDRAM device. There is a set of steps in a sequence to initialize the SDRAM Controller after a successful reset.
- Setup HMATRIX to enable the SDRAMC
- Initialize the SDRAMC and timing characteristics for your specified device.
- Configure your PIO controller(Parallel Input Output controller).
What is HMATIX?
The SDRAM is connected to the EBI. HMATRIX is the AHB bus Matrix that connects every controller on the bus to the core CPU. The SDRAMC is not selected by default, but it will have to be enabled. This is done by setting one of the special function registers for your device. The registers are named sfrX and are found in the HMATRIX module.
The below mentioned registers must be configured correctly to make sure SDRAM work correctly.
SDRAMC_MR, SDRAMC_CR, SDRAMC_TR, SDRAMC_HSR, SDRAMC_LPR, Interrupt registers, SDRAMC_MDR.
I hope, you got something about SDRAM. Check out the other tutorials.
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