Shift Registers explained

Hi friends today we are going to start one of the most important tutorials in embedded, Shift Registers. For this tutorial I assume that you have basic knowledge of electronics and gates.A shift register is a sequential logic device made up of flip-flops that allows parallel or serial loading and serial or parallel outputs as well as shifting bit by bit. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop.  Most of the registers possess no characteristic internal sequence of states.  All the flip-flops are driven by a common clock, and all are set or reset simultaneously.

Basic shift register functions:

  • SERIAL DATA TRANSMISSION- transfer of data from one place to another one bit at a time.
  • PARALLEL DATA TRANSMISSION- simultaneous transfer of all bits of a data word from one place to another.
  • SISOSERIAL IN/SERIAL OUT- type of register that can be loaded with data serially and has only one serial output.
  • SIPOSERIAL IN/PARALLEL OUT- type of register that can be loaded with data serially and has parallel outputs available.
  • PISOPARALLEL IN/SERIAL OUT- type of register that can be loaded with parallel data and has only one serial output.
  • PIPOPARALLEL IN/PARALLEL OUT- type of register that can be loaded with parallel data and has parallel outputs available.

Common Task of Shift Registers is as follows:

–        Serial/parallel data conversion

–         UART (an example)

–         Time delay

–         Ring counter

–         Twisted-ring counter or Johnson counter

–         Memory device

In this tutorial we are going to discuss about 74HC595, a universally famous shift register. This is a 8-bit shift register with output latches.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode lamps to VCC and ground.


How shift register works?
Shift Registers take a signal from one wire and output that information to many different pins. In this case, there is one data wire that takes in the data and 8 pins that are controlled depending on what data has been received. To make things better, there is an out pin for each shift register that can be connected to the input pin of another shift register. This is called cascading (daisy chain

) and makes the expansion potential an almost unlimited prospect.

One greater thing is that the shift register has this pin called RCLK or register clock. You can hold this pin LOW while you get everything setup and nothing on the display pins will change. Then when you are done, and everything is how you want, you pull the RCLK HIGH and the 74HC595 will display the new settings. So even though we are changing values in the register in 8 steps, it looks like it was just one step.

There are two pins you can use for cascading, Os and Os1. Os is for fast rising clocks and Os1 is for slow rising clocks. Hook this pin to the data pin of the next shift register and the overflow from this chip will be entered into the next.

The Control Pins
Shift registers have 4 control pins:

  • Latch – This pin tells the shift register when it is time to switch to newly entered data
  • Data – The 1’s and 0’s telling the shift register what pins to activate are received on this pin.
  • Clock – This is a pulse sent from the microcontroller that tells the shift register to take a data reading and move to the next step in the communication process
  • Enable Output – This is an on/off switch, High=On, Low=Off

What we need to use it?
Apart from power you need only three connections to start this functioning. To know in depth about all the pins please follow datasheet or click here to download it. Follow we are discussing in brief about 74HC695. The 74HC595 is a pretty cool little package

The pin out  goes like this:

Pin 1 – Output B – source for LED (+)
Pin 2 – Output C – source for LED (+)
Pin 3 – Output D – source for LED (+)
Pin 4 – Output E – source for LED (+)
Pin 5 – Output F – source for LED (+)
Pin 6 – Output G – source for LED (+)
Pin 7 – Output H – source for LED (+)
Pin 8 – GND
Pin 9 – Serial Output – Carries Value from Output H to Data Pin (pin 14) of another 74HC595 to create a chain of SR’s.
Pin 10 – Shift Register RESET – Active LOW clears data in Shift Register, Latch Register is no affected.
Pin 11 – Shift Clock – LOW to HI transition shifts in data (0 or 1) from the Data Pin (pin 14). This can be toggled very fast in applications where you want a fast refresh rate like displays. I think you can toggle it on the order of 1000Hz +
Pin 12 – Latch Clock – LOW to HI transition latches the SR data to the outputs – The latch in our case will be triggered after every 8th bit is shifted in.
Pin 13 – Output Enable – Active LOW – Allows data in the Latch Register to show on the display. Typically this will be kept low, so you could just hard-wire it, but I have the AVR setup to control it.
Pin 14 – Serial Data In (Data Pin) – Don’t be scared by the word “serial”. It just means digital 1 or 0 on a single pin. This is where the AVR will feed in the bits
Pin 15 – Output A – source for LED (+)  – It’s a weird spot for it but it works
Pin 16 – VCC 2.0-7.0 VDC

Making it do your bidding:
Follow following steps to get it work:

Step 1: Set Latch, Data, and Clock low

  • Setting the Latch low tells the shift register we are about to write to it.

Step 2: Set Data pin to the logic value you want to send to the Shift Register
Step 3: Set Clock pin high, telling the Shift Register to read in the current Data pin value

  • All other values currently in the Shift Register will move over by 1 place, making room for the current logic value of the Data pin.

Step 4: Set the Clock pin Low and repeat steps 2 and 3 until all data has been sent to the shift register.

  • The clock pin must be set low before changing to the next Data value. Toggling this pin between high and low is what creates the “clock pulse” the shift register needs to know when to move to the next step in the process.

Step 5: Set Latch high

  • This tells the shift register to take all of the data that has been shifted in and use it to activate the output pins. This means that you will not see data as it is shifting in; no change in the output pins will occur until the Latch is set high.

Step 6: Set Enable Output high

  • There will be no pin output until the Enable Output is set to high, no matter what is happening with the other three control pins.
  • This pin can always be left high if you wish

In next tutorial I will show you how to use 74HC595 with a AVR ATtiny13.

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About author

This article was written by admin

Admin has over twenty years experience in the electronics industry, largely dedicated to embedded software. A frequent presenter at conferences and seminars and author of numerous technical articles. Working presently as Development Manager in India. A firm Believer in Knowledge grows when it shared.


Comments (1)
  1. gman says - Posted: February 17, 2013

    Can u plz explain this line-“If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register.”

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